1. Field of the Invention The present invention relates to an overflow detection system and its circuit for use in addition and subtraction by a digital operating unit.
2. Description of the Prior Art
Conventionally, an overflow signal as to the results of addition and subtraction of two digital values has been detected using a carry signal obtained as a result of addition and subtraction or during operation.
FIG. 1 shows an adder for adding digital values expressed as n-bit 2's complements according to the ripple carrying system. a.sub.i is the ith value of augend A, b.sub.i is the (i)th value of addend B, c.sub.i is the (i)th carry output signal, and s.sub.i is the (i)th sum output. a.sub.n-1 and b.sub.n-1 are respectively a sign part of augend A and addend B and the following bits form a numeric part. The adder body is formed by connecting n sets of full adders 100 each of which enters the (i)th bit values of the augend and addend and the (i-1)th bit carry signal output and outputs the (i)th bit sum and the carry signal. The overflow signal is obtained by the exclusive OR circuit 101 which uses the carry signal c.sub.n-1 from the sign part and the carrY signal c.sub.n-2 from the MSD of the numeric part as inputs.
Also in case the expression method of negative numerals other than the 2's complement is adopted, the overflow of the result of addition is detected the carry signal from the sign part and the carry signal from the MSD of the numeric part.
However, the conventional overflow detection method is disadvantageous in that the overflow has been determined at the same time or after the result of sum was obtained since the overflow has been detected from the result of addition and the carry signal.